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SPT5240
10-bit, 400 MWPS Current Output Digital-to-Analog Converter
Features
* 400 MWPS update rate * Complementary current outputs * +3.3 V power supply * Low power dissipation: 149mW (typ) @CLK = 400MHz and 12mA output * Excellent AC performance: SFDR = 58dBc for CLK = 400MHz and OUT = 1.27 MHz * Internal reference
Description
The SPT5240 is a 10-bit digital-to-analog converter that performs at an update rate of 400M words per second. The architecture achieves excellent high-frequency performance with very low power dissipation. This makes it ideal for all types of battery-operated equipment requiring high-speed digital-to-analog conversion. The SPT5240 operates over an extended industrial temperature range from -40C to +85C and is available in a 32-lead LQFP package.
Applications
* Battery-operated devices * Portable RF devices * Set top boxes * Video displays * Broadband RF * High-speed test equipment
Functional Block Diagram
PWD DVDD AVDD
ISET
Reference Circuit
D0 - D9
10 Bits
10-bit Current Output DAC
IOP
ION
CLK
DGND
AGND
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DATA SHEET
SPT5240
Electrical Specifications
(TA = 25C, AVDD = 3.3V, DVDD = 3.3V, OUT = 1.27MHz, CLK = 400MHz, Clock Duty Cycle = 50%, IOUT = 20mA, RL = 50; unless otherwise noted) Parameter DC Performance Resolution Differential Linearity Error (DLE) Integral Linearity Error (ILE) Offset Error Full Scale Error Gain Error Maximum Full Scale Output Current Output Compliance Voltage Output Impedance Gain Error Tempco AC Performance Maximum Clock Rate Glitch Energy Settling Time (tsettling) Output Rise Time Output Fall Time Output Delay Time (tD) Spurious Free Dynamic Range (SFDR) Total Harmonic Distortion (THD) Digital and Clock Data Input VIH Minimum VIL Maximum Logic "1" Current Logic "0" Current Input Setup Time (tS) Input Hold Time (tH) Clock Feedthrough TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. LEVEL I IV V TEST PROCEDURE 100% production tested at the specified temperature. Parameter is guaranteed by design or characterization data. Parameter is a typical value for information purposes only. See Figure 1 See Figure 1 V V I I V V V -10 -10 1 1 -29 2 1 +10 +10 V V A A ns ns dBFS See Figure 1 Major code transition See Figure 1, major code trans. IV V V V V V V V 400 7 7.5 1.3 1.5 1.8 58 -55 MHz pV-s ns ns ns ns dBc dBc Full-scale output DC at ION DC at ION DC at both outputs DC at both outputs DC at both outputs I I I I I V V V V -1 -4 -.005 -15 -15 30 1.5 250 300 1.34 10 2 4 +15 +15 Bits LSB LSB %FS %FS mA V k ppm FS/C Conditions Test Level Min Typ Max Units
+.005 %FS
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SPT5240
DATA SHEET
Electrical Specifications (Continued)
(TA = 25C, AVDD = 3.3V, DVDD = 3.3V, OUT = 1.27MHz, CLK = 400MHz, Clock Duty Cycle = 50%, IOUT = 20mA, RL = 50; unless otherwise noted) Parameter Power Supply Requirements Supply Voltage Supply Current Sleep Mode AVDD DVDD Power Dissipation 25MHz Clock 25MHz Clock 20mA IOUT 12mA IOUT TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. LEVEL I IV V TEST PROCEDURE 100% production tested at the specified temperature. Parameter is guaranteed by design or characterization data. Parameter is a typical value for information purposes only. V V IV V 170 9.5 200 195 149 215 mA A mW mW AVDD = DVDD IV 3.0 +3.3 3.6 V Conditions Test Level Min Typ Max Units
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DATA SHEET
SPT5240
Absolute Maximum Ratings (beyond which the device may be damaged)
Parameter Supply Voltage AVDD DVDD Voltage Difference between AGND and DGND Voltage Difference between AVDD and DVDD Input Voltages D0 - D9 CLK Junction Temperature Lead, soldering (10 seconds) Storage Temperature Thermal Resistance (JA) for 32 lead LQFP -65 64 -0.5 -0.5 DVDD +0.5 DVDD +0.5 150 260 +150 V V C C C C/W -0.5 -0.5 3.7 3.7 0.5 0.5 V V V V Min Max Units
Note: Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications.
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SPT5240
DATA SHEET
Typical Performance Characteristics
(TA = 25C, AVDD = 3.3V, DVDD = 3.3V, OUT = 1.27MHz, CLK = 400MHz, Clock Duty Cycle = 50%, IOUT = 20mA, RL = 50; unless otherwise noted)
AC Performance vs. Clock Frequency
65 60 55 50
THD SNR SFDR
AC Performance vs. Temperature
65
Clock frequency = 327MHz SFDR
60
THD
55
dB
45 40 35 30 25 0 100 200 300 400 500 600
dB
50
SNR
45 40 -50 -25 0 25 50 75
Clock Frequency (MHz)
Temperature (C)
AC Performance vs. VDD
65 60 55
SFDR
Intergral Nonlinearity vs. Code
2.0 1.5
THD
50 45 40 35 3.0 3.3 3.6
SNR
LSB's
1.0 0.5 0 -0.5 0 128 256 384 512 640 768 896 1024
dB
VDD (V) Differential Nonlinearity vs. Code
0.6 0.4 35 0.2 45
AVDD
Code
AVDD, DVDD vs. Clock Frequency
LSB's
0 -0.2 -0.4 -0.6 0 128 256 384 512 640 768 896 1024
mA
25
15
DVDD
5 40 105 205 245 328 400
Code
Clock (MHz)
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DATA SHEET
SPT5240
Specification Definitions
Differential Linearity Error (DLE) or Differential Nonlinearity (DNL)
In an ideal DAC, output transitions between two adjacent codes are 1 LSB apart. Differential Linearity Error is the deviation, expressed in LSBs, from this ideal value.
Compliance Voltage
The maximum terminal output voltage for which the device will provide the specified current output characteristics.
Harmonic
1. Of a sinusoidal wave, an integer multiple of the frequency of the wave. Note: The frequency of the sine wave is called the fundamental frequency or the first harmonic, the second harmonic is twice the fundamental frequency, the third harmonic is three times the fundamental frequency, etc. 2. Of a periodic signal or other periodic phenomenon, such as an electromagnetic wave or a sound wave, a component frequency of the signal that is an integer multiple of the fundamental frequency. Note: The fundamental frequency is the reciprocal of the period of the periodic phenomenon.
Integral Linearity Error (ILE) or Integral Nonlinearity (INL)
The ideal transfer for a DAC is a straight line drawn between "zero-scale" output and "full-scale" output. ILE is the deviation of the output from the straight line. The deviation of the output at each code is measured and compared to the ideal output at that code. ILE may also be expressed as a sum of DLE starting from code 0...0 to the code that ILE measurement is desired.
Total Harmonic Distortion (THD)
The ratio of the sum of the power of first 9 harmonics above the fundamental frequency to the power of the fundamental frequency. Usually expressed in dBc.
Monotonic
A digital-to-analog converter is considered monotonic if the analog output never decreases as the code value at the input increases. A DLE less than -1 LSB would indicate a non-monotonic DAC.
Spurious Free Dynamic Range (SFDR)
The ratio of the fundamental sinusoidal power to the power of the single largest harmonic or spurious signal within the range of the 9th harmonic.
Offset Error
The deviation, from ideal, at the DAC output when set to zero-scale. In the current output DAC there should be no current flow at zero-scale. Therefore, Offset Error is the amount of current measured with the DAC set to zero-scale.
Clock Feedthrough
The ratio of the full-scale output to the peak-to-peak noise generated at the DAC output by input clock transitions. Expressed in dBFS.
Full-Scale Error
The ideal maximum full-scale current output of the DAC is determined by the value of RSET. Full-scale error is the deviation of the output from ideal with the offset error included.
Major Code Transition
The DAC code transition between 011...1 and 100...0 is referred to as major code transition. This transition often involves maximum number of internal circuit elements to switch states, resulting in worst DLE, ILE, glitch, etc.
Gain Error
The ideal maximum full-scale current output of the DAC is determined by the value of RSET. Gain error is the deviation of the output from ideal with the offset error removed.
Glitch Energy
A glitch is a switching transient that appears in the output of a DAC during a code transition. Glitch energy is measured as a product of the output voltage and time duration for major code transition, expressed in pV-s.
Full-Scale Output
The maximum current output available for a given value of RSET. In the SPT5240 IOP is full-scale at code 1111111111 and ION is full-scale at code 0000000000.
Output Rise Time
The amount of time for the output to change from 10% to 90% of the full-scale voltage, for a positive full scale transition from zero-scale to full-scale.
Zero-Scale Output
The minimum current output, ideally zero amps. In the SPT5240 IOP is zero-scale at code 0000000000 and ION is zero-scale at code 1111111111.
Output Fall Time
The amount of time for the output to change from 90% to 10% of the full-scale voltage, for a negative full scale transition from full-scale to zero-scale.
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SPT5240
DATA SHEET
Pin Configuration
DGND DVDD DVDD D3 D4 D5 D6 D7
Pin Assignments
Analog Outputs IOP DAC current output. Full-scale output at 11...11 input code. Complementary current output. Full-scale output ION at 00...00 input code. Digital Inputs D0 - D9 Digital inputs (D0 = LSB). PWD Power down mode pin. Active high. Internally pulled down. CLK Clock input pin. Data is latched on the rising edge. Reference ISET Full-scale adjust control. Connection for reference-current setting resistor. Power AGND DGND AVDD DVDD N/C Analog Supply Ground. Digital Supply Ground. Analog +3.3V supply. Digital +3.3V supply. No Connect
32
31
30
29
28
27
26
D2 D1 DVDD D0 DGND CLK DGND AGND
1 2 3 4 5 6 7 8
25
24 23 22
D8 DGND D9 DGND PWD AVDD AGND ISET
SPT5240SIT 32-pin LQFP
21 20 19 18 17
10
11
12
13
14
15 AVDD
IOP
ION
AVDD
AGND
AGND
Theory of Operation
The SPT5240 is a 10-bit 400 MWPS digital-to-analog converter. It integrates a DAC core with a bandgap reference and operates from a +3.3V power supply. The DAC architecture is a compound differential current output DAC consisting of a 6-bit fully segmented DAC for the MSBs and a 4-bit fully segmented DAC for the LSBs. The input cell, followed by a master-slave latch, buffers the digital inputs. A 6:64 decoder decodes the digital data for the MSBs, and a 4:16 decoder does so for the LSBs. The
N CLK
tS tH
AGND
N/C
16
9
outputs of the decoders are latched using a second bank of master-slave latches whose outputs then drive differential current switches, which steer the appropriate current to the IOP or ION outputs. The analog (AVDD) and digital (DVDD) power supplies are separated on chip to allow flexibility in the interface board. The analog (AGND) and digital (DGND) are separated on chip. Circuit board ground planes should be separated and tied together with a ferrite bead.
N+1
Digital Inputs
N
N+1
tD
N+2
N+3
VOP
1 LSB
N-2 VON
N-1
N
N+1
1 LSB tsettling
NOTE: Not to scale. For definition purposes only.
Figure 1: Timing Diagram
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DATA SHEET
SPT5240
IOUT Adjust
Sleep Mode Select
RSET
Clock In
CLK ISET PWD IOP VOP
50 10-bit Data Bus
DGND DVDD
SPT5240
50
AGND AVDD
ION VON
0.01F 0.1F
FB
0.01F 0.1F + + 10F
10F
Notes: 1. FB = Ferrite Bead across analog and digital ground planes. Place as close to DAC as feasible. 2. Minimum resistance (RSET) from ISET to ground relsults in maximum current output. 3. PWD pin has an internal pull-down resistor. Set pin high to initate sleep mode. 4. Outputs (IOP and ION) require minimum 5 load.
+D3.3V
+A3.3V
Figure 2: Typical Interface Circuit Diagram
Typical Interface Circuit
The SPT5240 requires few external components to achieve the stated performance. Figure 2 shows the typical interface requirements when used in normal circuit operation. The following sections provide descriptions of the major functions and outline performance criteria to consider for achieving optimal performance. Digital Inputs The SPT5240 has a 10-bit-wide parallel data input designed to work at +3.3V CMOS levels. Fast edges and low transients provide for improved performance. Clock Input The SPT5240 is driven by a single-ended clock circuit. In order to achieve best performance at the highest throughput, a clock generation circuit should provide fast edges and low jitter. Input Protection All I/O pads are protected with an on-chip protection circuit. This circuit provides robust ESD protection in excess of 3,000 volts, in human body model, without sacrificing speed.
Power Supplies and Grounding The SPT5240 may be operated in the range of 3.0 to 3.6 volts. Normal operation is recommended to be separate analog and digital supplies operating at +3.3 volts. All power supply pins should be bypassed as close to the package as possible with the smallest capacitor closest to the device. Analog and digital ground planes should be connected together with a ferrite bead as shown in Figure 2 and as close to the DAC as possible. Sleep Mode To conserve power, the SPT5240 incorporates a power down function. This function is controlled by the signal on pin PWD. When PWD is set high, the SPT5240 enters the sleep mode. The analog outputs are both set to zero current output, resulting in less than 10mA current draw from the analog supply. For minimum power dissipation, data and clock inputs should be set to logic low or logic high. Reference The SPT5240 utilizes an on-chip bandgap reference to set full-scale output current level. The current reference to the DAC circuitry is set by the external resistance value between the ISET pin and analog ground.
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SPT5240
DATA SHEET
IOUT (mA)
Analog Outputs The SPT5240 provides differential current outputs which provide an output level based on the value of RSET at maximum output code (see Figure 3). The required value of RSET may be calculated using the formulas: LSB = IFS/1023 Then: RSET = 1.111 - (1000 * LSB) 4 * LSB Where IFS is the desired full-scale current output. Each output requires a minimum 5 load to analog ground. The typical circuit utilizes 50 loads to develop voltage for the output transformer (refer to EB5240 data sheet). Table 1: Input Data Format Input Code D9 - D0 Analog Output ION 0000000000 1111111111 Sleep XXXXXXXXXX X indicates either data state. FS 0 0 IOP 0 FS 0
35
RSET Steps = 2.75k
30 25 20 15 10 5 0 60.3 11.2
RSET Value (k)
Figure 3: RSET vs. IOUT
Package Dimensions
LQFP-32
A B G H Symbol Min
INCHES
Max
MILLIMETERS
Min Max
CD
I J E F
A B C D E F G H I J K L
0.346 0.272 0.346 0.272 0.031 0.012 0.053 0.002 0.037 0 0.020
0.362 0.280 0.362 0.280 Typ 0.016 0.057 0.006 0.041 0.007 7 0.030
8.80 9.20 6.90 7.10 8.80 9.20 6.90 7.10 0.80 BSC 0.30 0.40 1.35 1.45 0.05 0.15 0.95 1.05 0.17 0 7 0.50 0.75
K L
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SPT5240
DATA SHEET
Ordering Information
Model SPT5240 Part Number SPT5240SIT Package 32-pin LQFP Container Tray Pack Qty -
Temperature range for all parts: -40C to +85C.

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